/* * File: DACmain_withInterrupts_v3 * Author: Zach Stauder * * Created on Mary 2, 2013, 7:10 PM */ #include #include #include #include #include #include "freqValues.h" /* * */ // _FOSC(FCKSM_CSECMD & OSCIOFNC_OFF & POSCMD_NONE); _FOSCSEL(FNOSC_FRC); //#define PORTCbits.RC8 = 1 SHUTDOWN_OFF //#define PORTCbits.RC8 = 1 SHUTDOWN_ON //long long analyzeInputs(long long inputs) { // // if((inputs&0x03)==0 { // standard mode (bits 0-1 for mode) // // long long outFreqs = (0x0000000007FFFFFC | inputs); // bits 2-26 for piano keys // outFreqs = outFreqs| // } //} //void initRamps(){ // //} unsigned char getI2CByte(){ unsigned char data; while(!I2C1STATbits.RBF); if(I2C1STATbits.D_A==0) // Wait until last byte was address data = I2C1RCV; return data; } void initiateI2C(){ I2C1BRG = 156; //132 // I21BRG = (1/I2C_CLK - 130ns)*SYS_CLK-2 // made clock 400 kHz // 156 makes it 100 kHz // made clock 400 kHz I2C1CONbits.I2CSIDL = 0; // operate in idle mode I2C1CONbits.IPMIEN = 0; // ????? I2C1CONbits.A10M = 0; // 7 bit slave address I2C1ADD = 0b1010101; // set 7 bit slave address I2C1CONbits.I2CEN = 1; // enable I2C module } void initiateInterrupts(void){ INTCON1bits.NSTDIS = 1; //Nested interrupts are not desired IEC1bits.SI2C1IE = 1; //Enable Slave Interrupt for I2C IFS1bits.SI2C1IF = 0; //Clear Slave Interrupt Flag } unsigned char address_rec = 0; unsigned char buttonStates1 = 0; unsigned char buttonStates2 = 0; unsigned char byteCount = 0; unsigned int freqs[36]; unsigned int eff[4]; unsigned char selection = 0; unsigned char recByte1 = 0; unsigned char recByte2 = 0; unsigned char recByte3 = 0; unsigned char recByte4 = 0; unsigned char recByte5 = 0; unsigned int numFreqs = 0; unsigned int multFactor = 1; unsigned int modulation = 0; void __attribute__((__interrupt__, no_auto_psv)) _SI2C1Interrupt(void) { IFS1bits.SI2C1IF = 0; // Clear Interrupt Flag if(I2C1STATbits.D_A==0){ //If last byte received was an address address_rec = I2C1RCV; //Unused variable to clear receive buffer byteCount = 0; } else if(I2C1STATbits.RBF==1){ //if receive buffer is full if(byteCount==0){ recByte1 = I2C1RCV; //Set data byte byteCount = byteCount+1; } else if(byteCount==1){ recByte2 = I2C1RCV; //Set data byte byteCount = byteCount+1; } else if(byteCount==2){ recByte3 = I2C1RCV; //Set data byte byteCount = byteCount+1; } else if(byteCount==3){ recByte4 = I2C1RCV; //Set data byte byteCount = byteCount+1; } else{ recByte5 = I2C1RCV; byteCount = 0; } freqs[0] = (recByte1&128)==128; freqs[1] = (recByte1&64)==64; freqs[2] = (recByte1&32)==32; freqs[3] = (recByte1&16)==16; freqs[4] = (recByte1&8)==8; freqs[5] = (recByte1&4)==4; freqs[6] = (recByte1&2)==2; freqs[7] = recByte1&1; freqs[8] = (recByte2&128)==128; freqs[9] = (recByte2&64)==64; freqs[10] = (recByte2&32)==32; freqs[11] = (recByte2&16)==16; freqs[12] = (recByte2&8)==8; freqs[13] = (recByte2&4)==4; freqs[14] = (recByte2&2)==2; freqs[15] = recByte2&1; freqs[16] = (recByte3&128)==128; freqs[17] = (recByte3&64)==64; freqs[18] = (recByte3&32)==32; freqs[19] = (recByte3&16)==16; freqs[20] = (recByte3&8)==8; freqs[21] = (recByte3&4)==4; freqs[22] = (recByte3&2)==2; freqs[23] = recByte3&1; freqs[24] = (recByte4&128)==128; freqs[25] = (recByte4&64)==64; freqs[26] = (recByte4&32)==32; freqs[27] = (recByte4&16)==16; freqs[28] = (recByte4&8)==8; freqs[29] = (recByte4&4)==4; freqs[30] = (recByte4&2)==2; freqs[31] = recByte4&1; freqs[32] = (recByte5&128)==128; freqs[33] = (recByte5&64)==64; freqs[34] = (recByte5&32)==32; freqs[35] = (recByte5&16)==16; eff[0] = (recByte5&8)==8; eff[1] = (recByte5&4)==4; eff[2] = (recByte5&2)==2; eff[3] = recByte5&1; numFreqs = 0; int i = 0; for(i=0;i<36;i++){ numFreqs = numFreqs+freqs[i]; } if(eff[0]==1){ modulation=0; } else if(eff[1]==1){ modulation=1; } else if(eff[2]==1){ modulation=3; } else{ modulation=0; } switch (modulation){ case 0: if(numFreqs==1){ multFactor=8; } else if(numFreqs==2){ multFactor=5; } else if(numFreqs==3){ multFactor=4; } else if(numFreqs==4){ multFactor=3; } else if(numFreqs==5){ multFactor=3; } else if(numFreqs==6){ multFactor=2; } else if(numFreqs==7){ multFactor=2; } else{ multFactor=1; } break; default: if(numFreqs==1){ multFactor=4; } else if(numFreqs==2){ multFactor=3; } else if(numFreqs==3){ multFactor=2; } else if(numFreqs==4){ multFactor=2; } else{ multFactor=1; } break; } } } int main(int argc, char** argv) { //set auxillary clock OSCCONbits.COSC = 0b001; // set clock to fast RC oscillator 7.37 MHz, divide by n, PLL OSCCONbits.NOSC = 0b001; // new oscillator selection bits FRC oscillator, divide n, PLL (pg 147) PLLFBDbits.PLLDIV = 59; // clock multiplier n+2 CLKDIVbits.FRCDIV = 0; // clock divider = 1 CLKDIVbits.PLLPOST = 0; // divide clock by two (2^(n+1)) CLKDIVbits.PLLPRE = 2; // divide clock by four (n+2) //Fosc = 7.37MHz*(59+2)/(4*2*1) = 56.196MHz // need 256*44.1kHz*5 = 56448000 OSCTUNbits.TUN = 1; // tune clock up .375 percent //Fosc = 7.37*1.00375*(59+2)/(4*2*1) = 56.4 MHz // Clock switch to incorporate PLL __builtin_write_OSCCONH(0x01); // Initiate Clock Switch to // FRC with PLL (NOSC=0b001) __builtin_write_OSCCONL(0x01); // Start clock switching while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur ACLKCONbits.AOSCMD = 0; // auxillary clock disabled ACLKCONbits.SELACLK = 0; // auxillary clock selects FOSC as source ACLKCONbits.APSTSCLR = 7; // divide by 1 DAC1CONbits.DACSIDL = 1; // stop DAC module in idle mode DAC1CONbits.AMPON = 0; // disable analog ouput amplifier in sleep/idle mode DAC1CONbits.FORM = 1; // signed ints, midpoint at 0x8000 DAC1CONbits.DACEN = 1; // enable DAC DAC1CONbits.DACFDIV = 9; // divide auxillary clock by 10 for DAC clock // The clock needs to be 256 times the sampling rate // making the clock 11.289 MHz // 56.4 Mhz/10/256*2 = 44100 Hz DAC1STATbits.LOEN = 0; // left channel output DAC disabled DAC1STATbits.LMVOEN = 0; // left channel midpoint DAC output disable DAC1STATbits.LITYPE = 0; // left channel interrupt if FIFO empty //DAC1STATbits.LFULL = 1 if full, 0 if not full, read only //DAC1STATbits.LEMPTY = 1 if empty, 0 if not, read only DAC1STATbits.ROEN = 1; // right channel output DAC enabled DAC1STATbits.RMVOEN = 1; // right channel midpoint DAC output enable DAC1STATbits.RITYPE = 1; // right channel interrupt if FIFO empty TRISCbits.TRISC8 = 0; // OUTPUT PORTCbits.RC8 = 1; // SET AS HIGH, SHUTDOWN OFF //DAC1STATbits.RFULL = 1 if full, 0 if not full, read only //DAC1STATbits.REMPTY = 1 if empty, 0 if not, read only DAC1DFLT = 0x0000; // default DAC output DAC1RDAT = 0x0000; // right data register DAC1LDAT = 0x0000; // left data register // int ramp[C1pts]; //int increments[36] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; //int mods[36] = {C1pts,C1Spts,D1pts,D1Spts,E1pts,F1pts,F1Spts,G1pts,G1Spts,A1pts,A1Spts,B1pts, // C2pts,C2Spts,D2pts,D2Spts,E2pts,F2pts,F2Spts,G2pts,G2Spts,A2pts,A2Spts,B2pts, // C3pts,C3Spts,D3pts,D3Spts,E3pts,F3pts,F3Spts,G3pts,G3Spts,A3pts,A3Spts,B3pts}; //unsigned int freqs[36]; int c1i=0; int c1si=0; int d1i=0; int d1si=0; int e1i=0; int f1i=0; int f1si=0; int g1i=0; int g1si=0; int a1i=0; int a1si=0; int b1i=0; int c2i=0; int c2si=0; int d2i=0; int d2si=0; int e2i=0; int f2i=0; int f2si=0; int g2i=0; int g2si=0; int a2i=0; int a2si=0; int b2i=0; int c3i=0; int c3si=0; int d3i=0; int d3si=0; int e3i=0; int f3i=0; int f3si=0; int g3i=0; int g3si=0; int a3i=0; int a3si=0; int b3i=0; int c1o=0; int c1so=0; int d1o=0; int d1so=0; int e1o=0; int f1o=0; int f1so=0; int g1o=0; int g1so=0; int a1o=0; int a1so=0; int b1o=0; int c2o=0; int c2so=0; int d2o=0; int d2so=0; int e2o=0; int f2o=0; int f2so=0; int g2o=0; int g2so=0; int a2o=0; int a2so=0; int b2o=0; int c3o=0; int c3so=0; int d3o=0; int d3so=0; int e3o=0; int f3o=0; int f3so=0; int g3o=0; int g3so=0; int a3o=0; int a3so=0; int b3o=0; int factor=1; int index; for (index = 0; index